Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yanos Sazeides. "BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers" in Journal of Parallel and Distributed Computing, January 2017. doi: 10.1016/j.jpdc.2017.01.016
Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, and Giorgos Dimitrakopoulos. 2016. An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. 13, 2, Article 22 (June 2016), 26 pages. doi: 10.1145/2930670
Marios Kleanthous, Yiannakis Sazeides, Emre Ozer, Chrysostomos Nicopoulos, Panagiota Nikolaou, and Zacharias Hadjilambrou. 2016. Toward Multi-Layer Holistic Evaluation of System Designs. IEEE Comput. Archit. Lett. 15, 1 (January 2016), 58-61. doi: 10.1109/LCA.2015.2445877
Davide Zoni and William Fornaciari, "Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators" in ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 3, Article 27, Pub. date: September 2015, doi: 10.1145/2751561
Dimitrios Rodopoulos, Georgia Psychou, Mohamed M. Sabry, Francky Catthoor, Antonis Papanikolaou, Dimitrios Soudris, Tobias G. Noll, and David Atienza. 2015. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations. ACM Comput. Surv. 47, 3, Article 38 (February 2015), 33 pages. doi: 10.1145/2678276
Davide Zoni, Federico Terraneo, and William Fornaciari. 2016. A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. J. Signal Process. Syst. 83, 3 (June 2016), 357-371. doi: 10.1007/s11265-015-0989-1
Patrick Bellasi, Giuseppe Massari, and William Fornaciari. 2015. Effective Runtime Resource Management Using Linux Control Groups with the BarbequeRTRM Framework. ACM Trans. Embed. Comput. Syst. 14, 2, Article 39 (March 2015), 17 pages. doi: 10.1145/2658990
Davide Zoni and William Fornaciari. 2015. Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. J. Emerg. Technol. Comput. Syst. 12, 3, Article 27 (September 2015), 24 pages. doi: 10.1145/2751561
D. Rodopoulos, F. Catthoor and D. Soudris, "Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS," in IEEE Computer Architecture Letters, vol. 14, no. 2, pp. 156-159, July-Dec. 1 2015. doi: 10.1109/LCA.2014.2385713
Rodopoulos, D.; Papanikolaou, A.; Catthoor, F.; Soudris, D., "Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane," IEEE Transactions onVery Large Scale Integration (VLSI) Systems, vol.PP, no.99, pp.1,1 doi: 10.1109/TVLSI.2014.2309663
P.Weckx, B.Kaczer, M.Toledano, P.Raghavan, J.Franco, P.Roussel, G.Groeseneken, F.Catthoor, "Implications of BTI-induced time-dependent statistics on yield estimation of digital circuits'', IEEE Trans. on Electron Devices, No.3, Vol.61, pp.666-673, March 2014. doi: 10.1109/TED.2013.2296358
Rodopoulos, D.; Weckx, P.; Noltsis, M.; Catthoor, F.; Soudris, D., "Atomistic Pseudo-Transient BTI Simulation with Inherent Workload Memory," IEEE Transactions onDevice and Materials Reliability, vol.14, no.2, pp.704,714, June 2014 doi: 10.1109/TDMR.2014.2314356
H.Kukner, K.Seyab, P.Weckx, P.Raghavan, S.Hamdouie, B.Kaczer, F.Catthoor, L.Van der Perre, R.Lauwereins, G.Groeseneken, "Comparison of Reaction-Diffusion and Atomistic Trap-based BTI Models for Logic Gates'', IEEE Trans. on Device and Materials Reliability, No.1, Vol.14, pp.182-193, March 2014. doi: 10.1109/TDMR.2013.2267274
Conference Papers
Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavřík and Vit Vondrak, "A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application," 5th Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES),HIPEAC 2017.
Zacharias Hadjilambrou and Yiannakis Sazeides, "How to make SMT Tail Latency Friendly ," Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017),HIPEAC 2017.
Portero, J. Sevcik, M. Golasowski, R. Vavrik, S. Libutti, G. Massari, F. Catthoor, W. Fornaciari, V. Vondrak, "Using an Adaptive and time predictable Runtime System for Power-Aware HPC-oriented applications", The Third Workshop on Low-Power Dependable Computing (LPDC) In conjunction with the 2016 International Green and Sustainable Computing Conference (IGSC) Nov. 7-9, 2016, Hangzhou, China. available online
Kuchar, S and Podhoranyi, M and Vavrik, R and Portero, A. "Dynamic computing resource allocation in online flood monitoring and prediction", IOP Conference Series: Earth and Environmental Science, vol. 39, number 1, pages 604-614, year 2016, IOP Publishing. available online
Corbetta, S. et al. "System-Wide Reliability Analysis on Real Processor and Application under Vdd and T Stress", SELSE 2016
M. Noltsis, P. Weckx, D. Rodopoulos, F. Cathoor and D. Soudris, "Accuracy of Quasi-Monte Carlo technique in failure probability estimations," 2016 International Conference on IC Design and Technology (ICICDT), Ho Chi Minh City, 2016, pp. 1-4. doi: 10.1109/ICICDT.2016.7542044
A. Kokolis, A. Mavrogiannis, D. Rodopoulos, C. Strydis and D. Soudris, "Runtime interval optimization and dependable performance for application-level checkpointing," 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp. 594-599. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7459381&isnumber=7459269
A. Scionti, S. Mazumdar and A. Portero, "Software defined Network-on-Chip for scalable CMPs," 2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, 2016, pp. 112-115. doi: 10.1109/HPCSim.2016.7568323
D. Hardy, I. Puaut and Y. Sazeides, "Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults," 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp. 91-96. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7459286&isnumber=7459269
William Fornaciari, Gianmario Pozzi, Federico Reghenzani, Andrea Marchese, and Mauro Belluschi. 2016. Runtime resource management for embedded and HPC systems. In Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms (PARMA-DITAM '16). ACM, New York, NY, USA, 31-36. doi: 10.1145/2872421.2893173
Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, and Marios Kleanthous. 2015. Modeling the implications of DRAM failures and protection techniques on datacenter TCO. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 572-584. doi: 10.1145/2830772.2830804
D. Zoni, L. Borghese, G. Massari, S. Libutti and W. Fornaciari, "TEST: Assessing NoC Policies Facing Aging and Leakage Power," 2015 Euromicro Conference on Digital System Design, Funchal, 2015, pp. 606-613. doi: 10.1109/DSD.2015.16
Portero, Antoni and Vavrik, Radim and Kuchar, Stepan and Golasowski, Martin and Vondrak, Vit and Libutti, Simone and Massari, Giuseppe and Fornaciari, William,"Flood prediction model simulation with heterogeneous trade-offs in high performance computing framework, 29th EUROPEAN Conference on Modelling and Simulation ECMS, 2015. available online
Halil Kükner, Pieter Weckx, Sébastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, and Guido Groeseneken. 2014. NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. In Proceedings of the 2014 17th Euromicro Conference on Digital System Design (DSD '14). IEEE Computer Society, Washington, DC, USA, 98-107. doi: 10.1109/DSD.2014.82
D. Rodopoulos et al., "HARPA: Solutions for dependable performance under physically induced performance variability," 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, 2015, pp. 270-277. doi: 10.1109/SAMOS.2015.7363685
Portero, Antoni and Vavrik, Radim and Kuchar, Stepan and Golasowski, Martin and Vondrak, Vit,"Run-time application developing phases for Energy trade-offs in HPC system node", International Conference of Electrical, Automation and Mechanical Engineering, EAME year 2015 available online
Antoni Portero, Radim Vavrik, Stepan Kuchar, Martin Golasowski, Simone Libutti, Giuseppe Massari, William Fornaciari, and Vit Vondrak. 2015. Simulation of a runoff model running with multi-criteria in a cluster system. In Proceedings of the Conference on Summer Computer Simulation (SummerSim '15), Saurabh Mittal, Il-Chul Moon, and Eugene Syriani (Eds.). Society for Computer Simulation International, San Diego, CA, USA, 1-8. URL: http://dl.acm.org/citation.cfm?id=2874950
G. Massari et al., "Harnessing Performance Variability: A HPC-Oriented Application Scenario," 2015 Euromicro Conference on Digital System Design, Funchal, 2015, pp. 111-116. doi: 10.1109/DSD.2015.87
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, and Zeljko Zilic. 2015. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI (GLSVLSI '15). ACM, New York, NY, USA, 57-62. doi: 10.1145/2742060.2742079
Davide Zoni, Federico Terraneo, William Fornaciari, "A control-based methodology for power-performance optimization in NoCs exploiting DVFS." J. Syst. Archit. 61, 5 (May 2015), 197-209. doi: 10.1016/j.sysarc.2015.04.004
Z. Hadjilambrou, M. Kleanthous and Y. Sazeides, "Characterization and analysis of a web search benchmark," 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA, 2015, pp. 328-337. doi: 10.1109/ISPASS.2015.7095818
Vavrik, Radim and Portero, Antoni and Kuchar, Stepan and Golasowski, Martin and Libutti, Simone and Massari, Giuseppe and Fornacciari, William and Vondrak, Vit, "Precision-Aware application execution for Energy-optimization in HPC node system", Presented at HIP3ES, 2015, pages 6, year 2015 URL: http://arxiv.org/abs/1501.04557
D. Stamoulis, D. Rodopoulos, B. H. Meyer, D. Soudris and Z. Zilic, "Linear regression techniques for efficient analysis of transistor variability," 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marseille, 2014, pp. 267-270. doi: 10.1109/ICECS.2014.7049973
Portero, Antoni and Kuchar, Vavrik, Radim and Golasowski, Martin and Vondrak, Vit, System and application scenarios for disaster management processes, the rainfall-runoff model case study, IFIP International Conference on Computer Information Systems and Industrial Management, pages 315--326, year 2014, Springer Berlin Heidelberg. URL: http://link.springer.com/chapter/10.1007%2F978-3-662-45237-0_30
A. H. Ashouri, G. Mariani, G. Palermo and C. Silvano, "A Bayesian network approach for compiler auto-tuning for embedded processors," 2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), Greater Noida, 2014, pp. 90-97. doi: 10.1109/ESTIMedia.2014.6962349
Portero, Antoni and Kuchar, Stepan and Vavrik, Radim and Golasowski, Martin and Massari, William Fornaciari and Vit Vondrak, "Framework for scheduling and resource management in time-constrained HPC application", 12th International Conference of Numerical Analysis and applied Mathematics, 2014, Rhodes, Greece, AIP Conf. Proc. 1648, 830013 (2015) doi: 10.1063/1.4913039
Gadioli, D.; Libutti, S.; Massari, G.; Paone, E.; Scandale, M.; Bellasi, P.; Palermo, G.; Zaccaria, V.; Agosta, G.; Fornaciari, W.; Silvano, C., "OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms," 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications, Milan, 2014, pp. 127-133. doi: 10.1109/ISPA.2014.25
N. Zompakis, I. Filippopoulos, P. G. Kjeldsberg, F. Catthoor and D. Soudris, "Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems," 2014 17th Euromicro Conference on Digital System Design, Verona, 2014, pp. 28-35. doi: 10.1109/DSD.2014.76
Marcello Farina, Davide Zoni, William Fornaciari, A control-inspired iterative algorithm for memory management in NUMA multicores, IFAC Proceedings Volumes, Volume 47, Issue 3, 2014, Pages 6117-6122, ISSN 1474-6670 doi: 10.3182/20140824-6-ZA-1003.02402
G. Massari et al., "Combining application adaptivity and system-wide Resource Management on multi-core platforms," 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, 2014, pp. 26-33. doi: 10.1109/SAMOS.2014.6893191
E. Paone, D. Gadioli, G. Palermo, V. Zaccaria and C. Silvano, "Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications," 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, Zurich, 2014, pp. 161-168. doi: 10.1109/ASAP.2014.6868651
Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, and Zeljko Zilic. 2016. "Capturing True Workload Dependency of BTI-induced Degradation in CPU Components". In Proceedings of the 26th edition on Great Lakes Symposium on VLSI (GLSVLSI '16). ACM, New York, NY, USA, 373-376. DOI: 10.1145/2902961.2902992 Poster: PDF
D.Rodopoulos, D.Stamoulis, D.Soudris, F.Catthoor, G.Liras, "Understanding Timing Impact of BTI/RTN with Massively Threaded Atomistic Transient Simulations'', International Conference on IC Design and Technology (ICICDT), Austin, Texas, May 28th- 30th, 2014. doi: 10.1109/ICICDT.2014.6838587
H.Kukner, M.El-khatib, S.Morrison, P.Weckx, P.Raghavan, B.Kaczer, F.Catthoor, L.Van der Perre, R.Lauwereins, G.Groeseneken, "Degradation Analysis of Datapath Logic Subblocks under NBTI Aging in FinFET Technology'', accepted for ISQED'14, Santa Clara CA, March 2014. doi: 10.1109/ISQED.2014.6783362
H.Kukner, P.Weckx, P.Raghavan, B.Kaczer, F.Catthoor, L.Van der Perre, R.Lauwereins, G.Groeseneken, "BTI reliability from Planar to FinFET nodes: Will the next node be more or less reliable?'', MEDIAN'14, colocated with DATE'14, Dresden, Germany, March 2014.
H.Kukner, P.Weckx, J.Franco, M.Toledano, M.J.Cho, B.Kaczer, P.Raghavan, F.Catthoor, L.Van der Perre, R.Lauwereins, G.Groeseneken, "Scaling of BTI reliability in presence of Time-zero Variability - Pathfinding from planar FET to advanced 3-D FinFET nodes'', accepted for IRPS'14, Hawai, June 2014.
P.Weckx, B.Kaczer, P.Raghavan, G.Groeseneken, F.Catthoor, P.Roussel, H.Kukner, "Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation-application to 6T SRAM'', accepted for IRPS'14, Hawai, June 2014.
Davide Zoni, Federico Terraneo and William Fornaciari, "An analytical, dynamic, power-performance router model for run-time NoC optimizations," 26th IEEE International SoC Conference (SOCC), September 04 – 06, 2013, Fraunhofer Institute for Integrated Circuits (IIS), Erlangen (near Nuremberg), Germany. doi: 10.1109/SOCC.2013.6749703
Y. Sazeides, E. Ozer, D. Kershaw, P. Nikolaou, M. Kleanthous, J. Abella, "Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes," in proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46), December 2013. doi: 10.1145/2540708.2540723
Federico Terraneo, Davide Zoni and William Fornaciari, "A cycle accurate simulation framework for asynchronous NoC design," International Symposium on System-on-Chip 2013, Tampere, Finland, October 23-24, 2013, (SoC 2013). doi: 10.1109/ISSoC.2013.6675263
Davide Zoni, Jose Flich and William Fornaciari, "Adaptive Routing and Dynamic Frequency Scaling for NoC Power-Performance Optimizations," (PATMOS 2013), in 23th International Workshop on Power and Timing Modeling, Optimization and Simulation, Karlsruhe, Germany, September 9-11, 2013. doi: 10.1109/PATMOS.2013.6662179
Davide Zoni and William Fornaciari, "A power gating design framework integrated in a cycle accurate simulator," in IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2013), August 5-7, 2013, Natal, Brazil.
Cristina Silvano, Gianluca Palermo, Sotirios Xydis and Ioannis Stamelakos. "Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon" In Proceedings of DATE 2014 - International Conference on Design, Automation and Test in Europe, Dresden, Germany. 24-28 March 2014. pp. 1-6. doi: 10.7873/DATE2014.214
Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, "DeSpErate: Speeding-up Design Space Exploration by using Predictive Simulation Scheduling". In Proceedings of DATE 2014 - International Conference on Design, Automation and Test in Europe. Dresden, Germany. 24-28 March 2014. pp. 1-4. doi: 10.7873/DATE2014.231
Giovanni Mariani, Gianluca Palermo, Roel Meeuws, Vlad-Mihai Sima, Cristina Silvano and Koen Bertels. "DRuiD: Designing Reconfigurable Architectures with Decision-making Support", In Proceedings of ASP-DAC 2014, 14th Asia and South Pacific Design Automation Conference, Singapore. January 2014. pp. 213-218. doi: 10.1109/ASPDAC.2014.6742892
Ioannis Stamelakos, Sotirios Xydis, Gianluca Palermo and Cristina Silvano. "Variation Aware Voltage Island Formation for Power Efficient Near-Threshold Manycore Architectures", In Proceedings of ASP-DAC 2014, 14th Asia and South Pacific Design Automation Conference. Singapore, January 2014. pp. 304-310. doi: 10.1109/ASPDAC.2014.6742907
Giuseppe Massari, Chiara Caffarri, Patrick Bellasi, and William Fornaciari. "Extending a Run-time Resource Management framework to support OpenCL and Heterogeneous Systems". In Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM '14) doi: 10.1145/2556863.2556868
Simone Libutti, Giuseppe Massari, Patrick Bellasi, and William Fornaciari. "Exploiting Performance Counters for Energy Efficient Co-Scheduling of Mixed Workloads on Multi-Core Platforms". In Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'14) doi: 10.1145/2556863.2556866
Workshops
Antoni Portero, et al, "Harnessing Performance Variability for HPC Applications", (Computer Architecture / Earth Sciences),IT4Innovations (Czech Republic), PRACE Scientific and Industrial Conference 2014, PRACE days14, Poster Session, Tuesday 20 May 2014.
Edoardo Paone, Giuseppe Massari, Patrick Bellasi, William Fornaciari, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria, "Combining Application Adaptivity and System-wide Resource Management: A novel approach", Poster in (PARMA-DITAM'14)
